Semiconductive device and method of operating same



1961 w. SHOCKLEY 2,997,604

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 13 Sheets-Sheet 1 I=l p n p I =-I E, b s c V =-V +V =-V FIG. II

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WILLIAM SHOCKLEY I INVENTOR.

ATTORN EYS Aug. 22, 1961 w. SHOCKLEY SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 13 Sheets-Sheet 2 D. C S

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WILLIAM SHOCKLEY INVENTOR.

ATTORNEYS Aug. 22, 1961. w. SHOCKLEY 2, 7,

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 15 Sheets-Sheet 3 FIG. 3.4

WILLIAM SHOCKLEY INVENTOR.

ATTORNEY Aug. 22, 1961 w. SHOCKLEY 2,997,604

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 13 Sheets-Sheet 4 I o co, 5 0% 1 l ,V

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WILLIAM SHOCKLEY INVENTOR.

ATTORNEYS 22, 1951 w. SHOCKLE'Y 2,997,604

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 13 Sheets-Sheet 5 p n P n 2 b b a F IG. 5 l

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a b s 0 WILLIAM SHOCKLEY INVENTOR.

ATTORNEYS Aug. 22, 1961 w. SHOCKLEY SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME l3 Sheets-Sheet 6 Filed Jan. 14, 1959 FIG. 7.I

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FIG. 7.3

WILLIAM SHOGKLEY INVENTOR.

BY f /ATTORNEYS FIG. 7.4

Aug. 22, 1961 w. SHOCKLEY 2,997,604

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME l3 Sheets-Sheet 7 Filed Jan. 14, 1959 FIG. 8.4

- WILLIAM SHOCKLEY INVENTOR.

' BY m w ATTORNEYS Aug. 22; 1961 w. SHOCKLEY SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME l5 Sheets-Sheet 8 Filed Jan. 14, 1959 FIG. 9.2

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WILLIAM SHOCKLEY INVENTOR.

Aug. 22, 1961 w. SHOCKLEY 2,997,604

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 13 Sheets-Sheet 10 D 5 I W FIG. IO.6

FIG. IOB .L v0 Z (b) FIG. IO.7

WILLIAM SHOCKLEY INVENTOR.

ATTORNEYS Aug. 22, 1961 W. SHOCKLEY SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 FIG. |O.9

l3 Sheets-Sheet l1 FIG. IO.I|

WILLIAM SHOCKLEY INVENTOR ATTORNEYS Aug. 22, 1961 w. SHOCKLEY 2,997,604

SEMICONDUCTIVE DEVICE AND METHOD OF OPERATING SAME Filed Jan. 14, 1959 No FIG. 10.15

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T C A T N m 0 n 0 V N C W W P! m m M w M H \.I\ R 0 m l NV M m 2 B III M w m F WILLIAM SHOCKLEY- INVENTOR.

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ATTORNEYS 2,997,604 SEMICONDUC DEVICE AND METHOD OF OPERATING SAME William Shockley, 23466 Corta Via, Los Altos, Calif. Filed Jan. 14, 1959, Set. No. 786,818 33 Claims. C1. 30788.5)

This invention relates generally to a semiconductive device and method of operating the same and more particularly to a two-terminal negative-resistance semiconductive device.

In principle, it is possible to make compositional structures in semiconductive crystals on a scale much smaller than is possible in vacuum tubes. However, presently available techniques are limited and it may be many years before the techniques are perfected to the extent that the required compositional structures for operating at very high frequencies can be made. The difficulty of making small structures increases with the number of electrodes which make up the structure.

Another inherent limitation in semiconductive devices presently in use is that they have limited frequency power characteristics. That is, as the devices are designed for higher frequencies of operation, the power handling capabilities are reduced. When the power handling capabilities are increased, the upper frequency limits are generally decreased.

Two terminal negative resistance devices may be used in conjunction with nonreciprocal elements to produce stable high gain amplifiers. Devices of this type may also be used in parametric amplifiers. Furthermore, suitable devices of this type may be employed in circuits which generate sharp pulses or which sharpen existing pulses. Other important uses of negative resistance semiconductive devices have been stressed in the literature and will not be enumerated.

It is a general object of the present invention to provide a semiconductive device exhibiting negative resistance and methods of operating the same.

It is another object of the present invention to provide a semiconductive device and method of operating the same for operation at relatively high power-frequency limits.

It is another object of the present invention to provide a semiconductive device and method of operating the same for operation at relatively high frequencies.

It is another object of the present invention to provide a semiconductive device and method of operating the same for operation at relatively high powers.

It is still another object of the present invention to provide a semiconductive device having maximum lateral area for stable operation.

It is still another object of the present invention to provide a semiconductive device and method of operating the same by impulsive charging.

It is still another object of the present invention to provide a method for operating semiconductor junction devices up to frequencies close to the limits set by the diffusion time through the base layers. A further important object is to maximize the power level at which this can be accomplished.

It is a further object of the present invention to provide a semiconductive device and method of operating the same in which the internal instabilities are minimized.

It is still a further object of the present invention to provide a semiconductive device which includes first and second surface layers of semiconductive material and an interior base region forming a junction with each of said layers, said base region including at least one layer and means for charging said base region substantially r Ice uniformly over its entire area in a time which is comparable to the diffusion time of majority carriers through the layer and if desired including means for removing majority carriers substantially uniformly from said base region.

It is another object of the present invention to provide a semiconductive device including a base region Which is uniformly charged in a time comparable to the diflfusion time of minority carriers through the region and which includes recombination centers in a transition region contiguous to the base region.

It is still another object of the present invention to provide a semiconductive device and method of operating the same so that negative resistance results from space charge narrowing of the base layer.

It is still another object of the invention to provide a four-layer semiconductive device from which substantially all of the carriers can be removed from the middle two layers by application of bias.

It is still another object of the invention to provide a semiconductive device and methods of operating it whereby A.-C. power generation does not depend upon variation of alpha with current density.

It is still a further object of the present invention to provide a novel method of operating four-layer semiconductive devices.

It is still a further object to use jointly two-layer diodes and transistor diodes with comparable carrier lifetimes in improved circuits.

It is another object of the present invention to provide a semiconductive device and method of operating the same which includes a base region which can generate current pulses having a duration of the order of the transit of carriers through its base region.

It is still another object to provide novel circuits which incorporate semiconductive devices in accordance with the invention.

These and other objects of the invention will become more clearly apparent from the following description when taken in conjunction with the accompanying draw- 1ngs.

Referring to the drawings:

FIGURE 1.1 shows a three-layer semiconductive device and the current and voltage conventions used in discussing its operation.

FIGURE 1.2 shows a graphical method of obtaining an approximate solution for the voltage-current relationship in a three-layer semiconductive device.

FIGURE 1.3 shows the voltage-current characteristics corresponding to the three-layer device of FIGURE 1.2.

FIGURE 1.4 shows a graphical method of obtaining the approximate solution for voltage-current relationship in a four-layer semiconductive device.

FIGURE 1.5 shows the voltage-current characteristics corresponding to the four-layer device of FIGURE 1.4.

FIGURE 1.6 shows a four-layer semiconductive device in accordance with the invention with space-charge narrowing of the base layer.

FIGURE 1.7 shows the voltage-current relationship for the four-layer device of FIGURE 1.6.

FIGURE 1.8 shows the voltage-current characteristics for a symmetric hook collector four-layer semiconductive device.

FIGURE 2.1 shows the current and voltage conventions used in analyzing the impedance of a three-layer device.

FIGURE 3.1 shows the load line solution for operation of devices in accordance with the invention.

FIGURE 3.2 shows the equivalent circuit for a threelayer device operating at relatively low frequencies.

FIGURE 3.3 shows a three-layer diode of cross-sectional dimensions L-L.

FIGURE 3.4 shows a pair of diodes having a corp,

& bined cross-sectional area equal to the single device shown in FIGURE 3.3.

FIGURE 3.5 shows the etfects of disturbance when there is an equal distribution of current in the device.

FIGURE 3.6 shows the lowest eigen-function for a rectangle with the long edge along the x-axis.

FIGURE 3.7 show a higher order eigen-function for a rectangular boundary.

FIGURE 5.1 shows the current and voltage conventions for determining the impedance of a four-layer device.

FIGURE 5.2 shows the current and voltage conventions for a four-layer device.

FIGURE 6.1 shows space-charge widening in a threelayer device.

FIGURE 7.1 shows a semiconductive device in accordance with the invention with a guard ring.

FIGURE 7.2 shows the lowest relevant eigen-function for the device of FIGURE 7.1.

FIGURE 7.3 shows a three-layer device including a rib structure.

FIGURE 7.4 shows a three-layer device having an interdigitated structure.

FIGURE 8.1 shows a three-layer device in accordance with the invention connected in an amplifier circuit.

FIGURE 8.2 shows the voltage-current relationships prevailing in FIGURE 8.1.

FIGURE 8.3 shows a pulse amplifying circuit including three-layer semiconductive devices in accordance with the invention.

FIGURE 8.4 shows a sharp pulse generator employing three-layer semiconductive devices in accordance with the invention.

FIGURES 9.1a-h show devices and the electric fields and carrier density in a four-layer diode.

FIGURES 9.2eu show the electric field and carrier density in a four-layer device at the steady state condition and after minority carrier extraction.

FIGURES 9.3a-c show the electric field and carrier density in a four-layer device in a condition of majority carrier extraction.

FIGURE 9.4 shows an unsymmetrical three-layer diode.

FIGURE 9.5 shows the current voltage characteristics for the diode of FIGURE 9.4.

FIGURE 10.1 shows an oscillator circuit employing a four-layer device in accordance with the present invention.

FIGURE 10.2 shows the voltage-current waveforms at various points in the circuit in FIGURE 10.1 during operation.

FIGURE 10.3 shows a driven oscillator incorporating a four-layer device.

FIGURE 10.4 shows a push-pull oscillator employing four-layer devices.

FIGURE 10.5 shows a high power bistable circuit incorporating four-layer devices.

FIGURE 10.6 shows another oscillator circuit which employ negative resistance devices operated in accordance with the invention.

FIGURE 10.7 shows the voltage and current waveform at various points in the circuit of FIGURE 10.6.

FIGURE 10.8 shows an approximation of the circuit of FIGURE 10.6 as one device is being turned on.

FIGURE 10.9 shows a circuit including negative resistance devices and saturable reactors.

FIGURE 10.10 depicts the role of majority carrier extraction in the oscillator ocf FIGURE 10.6.

FIGURE 10.11 shows how switching transistors depend on diode majorities.

FIGURE 10.12 shows the effect of lifetime on the switching cycle.

FIGURE 10.13 shows the relationship of emitter and collector junction charges.

FIGURE 10.14 shows the use of two-layer diodes to control majority carrier extraction.

FIGURE 11.3 schematically illustrates parallel connection of a plurality of circuits of the type shown in FIGURE 11.2.

FIGURE 11.4 shows a plurality of circuits of the type shown in FIGURE 10.6 connected for parallel operation.

FIGURE 12.1 shows a suitable means for constructing a three-layer device in accordance with the invention.

FIGURE 12.2 shows a device in accordance with the present invention being subjected to particle bombardment.

In general, novel semiconductive junction devices and methods of operating the same are described. Methods of operation and structures are disclosed for maximumizing the power level at which the high frequency operation can be achieved. In general, this can be achieved by uniform charging of the base layer. Broadly speaking, this may be accomplished by impulsive charging of the base layer so that internal stabilities do not occur or by limiting the size of the device and/ or introducing the edge effect characteristics.

The important features of the present invention have not been realized in the past. In Patent No. 2,855,524, a four-layer transistor diode is described suitable for operation as a transistor switch. For this purpose, uniform charging at high frequency is not important and quite adequate switches can be made in which avalanche multiplication occurs chiefly at the surface. Such devices switch at sufliciently rapid rates for their purpose, and when turned on, usually stay on long enough to have uniform conductance over their entire base layer. There is no mention in the patent nor in any of the literature relating to four-layer diodes of producing a structure in which a substantially uniform charging of the base layer is effected.

In order to facilitate the understanding of the inven tion, a description of the various mechanisms which enter into the operation of junction semiconductive devices in accordance with the invention are described. Since many aspects of the design are novel and cannot be appreciated by reference to published material, an extensive theoretical development is presented as a basis for the theory, design and operation of junction devices in accordance with the present invention. The description is related particularly to threeand four-layer two-terminal devices and is divided into twelve sections each having one or more subsections.

In general, the symbols employed have been defined as they are used and the symbols are consistent within each of the sections. For descriptive and mathematical simplicity, certain symbols are designated R for right, and L for left. Other designations are b for base, 6 for emitter, and c for collector, with s referring to spacecharge regions.

A brief summary of the contents of the sections follows:

Section 1 describes the manner in which negative differential resistance may arise in semiconductive devices. It is shown that negative resistance may arise by increasing multiplication in the collector space-charge region with increasing voltage, while at the same time or of the emitter-base combination increases with increasing current. Adjustment of the majority carrier current to control the shape of the voltage-current characteristics to provide a wide variety of characteristics for the twoterminal device is analyzed. It is shown that the negative ditferential resistance devices may be formed in which avalanche multiplication plays no significant role. This is achieved by having at least one of the base layers sufficiently doped and narrow that space-charge regions of the collector junction penetrates the layer to a significant degree. As the penetration increases due to increased voltage, increased current flows. There is a hook-collector action as the device exhibits negative resistance even though one of the emitter-base regions does not exhibit the characteristics of increasing a with increasing current.

The relationship between A.-C. and D.-C. parameters and the dependence of the various parameters on frequencies is analyzed in Section 2. The criterion for constructing devices for high frequency operation is derived. The upper frequency limit at which devices will exhibit negative differential resistance is defined. It is shown that the frequency response can be increased by having strong attenuation of injected carriers in the base layer.

The lateral stability problem for a three-layer device is discussed in Section 3. It is shown that it is possible to construct a device which has internal instability even though it is fed from a high resistance external source. The total current may not change but in one portion of the device, the change in collector current may be positive while in another it may be negative. The AC. voltage changes from one position of the device to another and excessive currents may be drawn at limited areas within the device. Thus, the device does not have lateral stability and may tend to burn out in spots due to ,this instability. The dimensions and conductance of the base layer for stable operation at small A.-C. signals is derived and defined.

Section 4 compares the response and operation of the device in accordance with the invention and a conventional transistor. It is shown that a device in accordance with the present invention has substantially constant impedance, independent of frequency, towards the upper frequency limit. It is shown that devices in accordance with the invention are simpler to manufacture and more inexpensive.

A discussion of the operation and stability, and complex impedance of a four-layer device is contained in Section 5. The problems are much the same as those discussed in Section 3; however, the analytical solutions are considerably more complex. It is reasoned that the conductance in mhos per square is of the order of twice the total device current in amps for a device operating stably at room temperature.

Section 6 discusses space-charge widening in threeand four-layer devices in accordance with the invention.

Section 7 shows that the lateral cross-sectional area of a device in accordance with the invention may be increased by employing a conductive ring surrounding the Working area. Examples of rib and web structures and interdigitated structures are given, together with quantitative limits as to size.

In Section 8 there is described impulsive operation of devices in accordance with the invention. It is shown that the current multiplication results and that the area limitation previously described is not applicable. With impulsive charging and sufiiciently high build-up, there is no time for instability to occur. It is shown that the build-up should be relatively high in comparison to the characteristic build-up time of a three-layer structure. There is described a pulse generating circuit incorporating impulsive charging. It is shown that the more rapid processes can be carried outwith limited area and punchthrough and avalanche multiplication occurring at the same voltage.

Section 9 discusses the novel concept of carrier extraction from a base layer by application of reverse bias. It is shown that the device is relatively insensitive to the dV/dt effect. It is also shown that a four-layer device may be operated at much higher frequencies when reverse voltage majority carrier extraction is employed.

In Section 10 some oscillator and amplifier circuits are shown which incorporate devices and methods in accordance with the invention. An extensive treatment of the SECTION 1.-HOW NEGATIVE RESISTANCE MAY ARISE IN TRANSISTOR DIODES 1A. A Discussion of a Negative Resistance Three-Layer Device 1B. Approximate Treatment of the Current Voltage Characteristic of a Four-Layer Diode 1C. A Transistor Diode with Negative Resistance Not Using Avalanche but Instead Using Space-Charge Narrowing of a Base Layer =1D. Symmetrical Hook collector Transistor Diode 1E. Other Forms of Negative Resistance Characteristic SECTION 2.The COMPLEX IMPEDANCE OF A THREELA\"ER TRANSISTOR DIODE 2A. Introduction 213. Notation and Functional Dependance of the Quantities Involved 2C. Notation for the Frequency Dependence 2D. The Collector Admittance 2E. Frequency Dependence of Alpha and the Admittance for a Uniform Base Layer The Relationship of the D.-C. Alpha and the Zero Frequency A.-C. Alpha 2G. The Impedance for Unit Area Measured at the Collector with the Base Floating SECTION 3.LATERAL STABILITY AND SIZE LIMITATION FOR A THREE-LAYER TRAN- SISTOR DIODE 3A. Introduction 3B. The Diode Stability Problem 3C. The Base Impedance in a Transistor Structure 3D. Simplified Model for Lateral Stability Problem 3E. The Lateral Stability Problem SECTION 4.CO'M-PARISON BETWEEN TRAN- SISTOR DIODE AND CONVENTIONAL TRAN- SISTOR SECTION 5.-COMPLEX IMPEDANCE AND LAT- ERAL STABILITY IN A FOUR-LAYER TRANSIS- TOR DIODE 5A. Introduction 5B. Diode Impedance SC. Case of Both Emitters Grounded 5D. Transients for g Near Stability Limit 5E. Form of Disturbance for Slow Solution SF. The Lateral Stability Condition SECTION 6.SPACE-CHARG E WIDENING IN THE FOUR-LAYER DIODE 6A. The Space-Charge Widening Effects in a Three- Layer Transistor 6B. Evaluationof the Space-Charge Widening Terms 60. Evaluation of the Impedance 6D. Comments on Lateral Stability SECTION 7.OTHER COMMENTS ON LATERAL STABILITY PROBLEM SECTION 8.-I MPULSIVE BASE CHARGING AND POWER 7 SECTION 9.-CARRIER EXTRACTION SECTION 10.40MB OSCILLATOR CIRCUIT PRINCIPLES 10A. Some Simple Oscillator Circuits 10B. A High Performance Push-Pull Oscillator Circuit 10C. The dV/dt Efiect 10D. Minority Carrier Extraction in the High Performance Circuit 10E. Majority Carrier Extraction 10F. The Switching Cycle 10G. Tolerances and Design Limits 10H. Conclusions SECTION l1.S ERIElS AND PARALLEL OPERATION SECTION l2.-4SOME MEANS OF PRODUCING STRUCTURES AND ADDITIONAL GENERAL COMMENTS SECTION 13. ILLUSTRATIVE DESIGN CALCULATIONS A detailed description of the invention follows.

SECTION 1.-HOW NEGATIVE RESISTANCE MAY ARISE IN TRANSISTOR DIODES ]A.-A discussion of a negative resistance three-layer device Some of the principles upon which negative resistance transistor diodes operate may be understood in terms of the behavior of a three-layer transistor diode. When such a diode is properly made in silicon, it exhibits a negative resistance portion of the current-voltage characteristic. The negative resistance arises from the fact thta avalanche multiplication in the collector space-charge region increases with increasing voltage while, at the same time, the alpha of the emitter-base combination increases with increasing current. This leads to behavior in which voltage decreases as current increases over certain ranges of current and leads to a negative clifierential resistance.

FIGURE 1.1 represents schematically a three-layer structure for use in a description of the mechanisms of operation. In keeping with customary transistor notation, the current into the emitter is denoted by I and the current into the base and collectors is similarly represented by I and I The current 1 is introduced for purposes of exposition; in two-terminal devices this current is zero. For the p-n-p device represented in FIG. 1.1, the convention for algebraic sign corresponds to positive signs for the operating condition so that positive current flow I is from emitter to collector in the diagram and positive applied voltage V produces a negative voltage in respect to ground upon the collector body.

In order to derive the current-voltage relation for this device, we consider a condition in which the voltage across the space-charge layer at the collector junction is V and the current in the emitter lead is zero. Under these conditions, a current will flow between base and collector which is denoted by I (V To a high degree of accuracy, this current is independent of the voltage across emitter junction. Furthermore, space charge due to currents in the collector region is small enough so that effects of the space charge upon multiplication in the space-charge region are usually negligible. On the basis of these assumptions, the total current across the spacecharge junction may be regarded as the sum of two terms: first, the current which would flow if the emitter current were zero and, second, that which is due to minority carriers injected by the emitter which diffuse through the base layer and arrive at the collector junction and are multiplied in crossing the space-charge layer.

When the device is operated as a two-terminal device, the emitter current and the collector current are equal in magnitude and the base current is zero. The total current crossing the space-charge region is equal to the '8 total current I flowing through the device. In accordance with the assumption of additivity, the relationship follows at once. In this equation the total current crossing the space-charge layer is considered as being due to the term I (V discussed above plus the multiplied injected current which reaches the space-charge region. The multiplication factor is denoted by M(V For purposes of exposition the voltage V will be used in the equations although, for all practical purposes, it is equal to the applied voltage across the device since, in general, the voltage across the space-charge junction is so large in comparison to the voltage across the emitter junction that the latter can be neglected in comparison.

In general, the current I (V is small compared to the currents when the device is in the operating or negative resistance condition. This leads directly to conclusions regarding the current-voltage relationship by relatively simple means. Solving Equation 1 for the current so that if I is very much larger than I (V then it is evident that the denominator in Equation 2 must be very small compared to unity. For this to be true, the relationship S) )=1 must hold.

As is well known for silicon devices, the alpha of emitter-base structures rises with increasing base current. See, for example, C. T. Sah, R. N. Noyce, and W. Shockley, Carrier Generation and Recombination in p-n Junctions and p-n Junction Charcteristics, Proc. IRE, vol. 45, No. 9, pp. 12284243, September 1957; J. L. Moll, M. Tanenbaum, J. M. Goldey, and N. Holonyak, P-n-p-n Transistor Switches, Proc. IRE, vol. 44, pp. l174ll82, September 1956; and, W. Shockley and I. F. Gibbons, Introduction to the 4-Layer Diode, Semiconductor Products, vol. 1, pp. 9-13, January-February 1958. This is believed to be due to diflYerent dependence upon voltage of the recombination current in the transistion region of the junction and the current injected into the base layer proper. We shall return to this point in a subsequent section. Thus, in Equation 3 04(1) is an increasing function of current over a portion of the current range. On

the other, M(V is an increasing function of voltage for all voltages up to the breakdown voltage, at which M approaches infinity. Thus, for any given value of I, there will be a value of M which satisfies Equation 3, and corresponding to this value M there will be a voltage lying between zero and the breakdown voltage. In the region where at of 1 is increasing with I, it follows that M and consequently V must be decreasing functions of current. A characteristic in which the voltage decreases with current gives rise to a negative differential resistance, and in this condition the diode may be used to produce A.-C. power when properly connected to a circuit and supplied with suitable D.-C. bias.

In order to design two-terminal transistor diodes, it is necessary to have methods for calculating their characteristics quantitatively and controlling the fabrication processes by means of a quantitative theory. A semi-quantitative theory adequate for most purposes may be developed using certain simplifying assumptions. These can be modified, if necessary, to produce a more exact theory. Only the simple theory is treated here, however, since it suflices to illustrate the main principles involved, and an exact theory is far more cumbersome and the physical effects are obscured by the analytical details.

The simplifying assumption which permits a relatively simple treatment of the current voltage characteristics consists of assuming that the current I (V consists of a saturated current which is substantially independent of voltage and which is then multiplied by the same multiplication factor as the current injected through the base Q layer. This is not exactly true since, first, the width of the space-charge region varies with reverse voltage and this increases the generation in the space-charge region and, second, carriers generated in the space-charge region are multiplied by a factor which depends upon the point of their origin in the space-charge region. Neither of these effects varies rapidly with voltage, however, compared to the variation of the multiplication factor M itself. For this reason, the principal effects are properly represented by assuming that Where the quantity I is regarded as a constant generated current. Using assumption (4) and dividing Equation 1 by I and by M leads to It is seen that Equation 5 has terms dependent only upon V on the left side of the equality sign, and terms dependent only upon I on the right side. Consequently, if the right side of Equation 5 is studied as a function of current, then for each value of current, the value of the multiplication factor can be found and consequently so can V In FIG. 1.2, we represent a plot on logarithmic axes of the righthand side of Equation 5. On such a plot, the term 1 appears as a line at 45 with a negative slope. The line for log oc(I) is represented as a line at 45 with positive slope. This corresponds to the assumption that over a certain range a(I) is represented y Ot(I)=I/I for I I (6) For larger values of I than 1 on is substantially constant. Also, for values of I so small that the voltage across the emitter junction is substantially less than thermal voltage, v =kT/ q, a(I) is substantially constant. This portion of the curve is not represented on FIG. 2.

The sum of the two terms on the right side of FIG. 2 is represented as a heavy line. It is seen that this heavy line has a minimum value at approximately the geometric mean of I and I This minimum value corresponds to the maximum value of M and consequently, maximum voltage V For values of I larger or smaller than this geometric mean value, M is smaller than its maximum value and V is also smaller than its maximum.

The behavior just discussed leads to the current voltage curve represented in FIG. 1.3, in which the voltage V is neglected compared to V so that the total voltage V is used in place of V As is seen there, for I greater than I M is greater than unity and V is correspondingly greater than zero. V rises to a maximum for I equal approximately to the (1 1 and V is less than this maximum value on either side of the maximum. These results may be summarized by:

Maximum V for l /I=1/I (7) 1: s e) A One of the conventional approximations for avalanche multiplication with V representing the breakdown or limiting voltage at the junction leads to the following condition at the maximum for voltage:

where AV is the amount by which V falls short of reaching V at the maximum. For example, if n=3 and I is 10- amperes and L is 1O amperes, the maximum will occur at 10" amperes and AV will be about 10 of V3.

The treatment just given for the determination of the current at the voltage and current maximum is based on the assumption that a is proportional to I near this maximum. A more general expression can be obtained by difierentiating Equation 1 in respect to I. At the maximum, V does not change in respect to I, so that at the maximum the condition must hold Combining this equation with Equation 1, we find that at the maximum the relationship This relationship reduces to Equation 8 if alpha is as sumed to be of the form given by Equation 6.

For currents much larger than I the voltage approaches a limiting value given by s B( max) where a is the maximum value of on for large currents.

1B.Appr0ximate treatment of the current voltage characteristic of a four-layer diode This section treats a four-layer diode in the simplified graphical form used in connection with the three-layer diode. This will illustrate another way in which negative resistance can arise and can also be used as a basis for comparing a new form of operation of four-layer diode with the conventional form. Proceeding as was done for Equation 1, the total current flowing through the device is assumed to consist of a multiplication of the current that would be generated if both emitter currents were zero plus the multiplication of the two injected currents which arrive at the center collector junction. This leads to where a (I) and a (I) apply to the junction at the left and at the right in a diagram like FIG. 6. (FIGURE 1.6 emphasizes space-charge narrowing of a base layer; an effect treated in Subsection 1D and neglected in this subsection.)

In Equation 1 we have again made the simplifying assumption that the multiplication factor M is the same for all currents and that the space-charge generated current is constant and independent of voltage.

If Equation 1 is divided by MI, we again obtain separation into Voltage-dependent and current-dependent terms.

Equation 2 may be analyzed by plotting the right-hand side of the equation as a functionof I upon logarithmic coordinate paper. This is represented in FIG. 1.4 where the term /1 is represented by line of 45 negative slope, While the two or terms are represented by rising lines which do not reach unity and which approach their limiting or values at two different points denoted by I for the :1 term and I for the ot term. Again, the sum of the terms on the right-hand side of Equation 2 is represented by a dark-solid line. It is seen that in this case the solid line crosses the zero axis of logarithms on the vertical scale, corresponding to the value 1 for M. This corresponds to zero voltage. Thus, for the four-layer diode there is a holding current at which the voltage goes substantially to zero.

The theory of the voltage dependence when the collector voltage drops to values small compared to thermal voltage is a separate subject and is not needed at this point in the discussion. In the on condition the fourlayer diode behaves much like three p-n junctions all biased forward in parallel.

In terms of the foregoing it can be seen how a variety of shapes of the current voltage curves may be produced. The curve corresponding to FIG. 1.4 is represented in FIG. 1.5, and it is seen that it exhibits a peak of voltage determined by I and I in much the same Way as the peak voltage of FIGS. 1.2 and 1.3 was determined. This is followed by a substantially flat portion in which a is constant and a is small. As 11 approaches unity, there is another drop, and the voltage approaches zero abruptly in the neighborhood of 1 The value at Which 11 V drops to Zero in accordance with the approximate Equation 2 is denoted by I and is called the holding current for four-layer diodes.

The behavior of the current-voltage characteristic for currents slightly less than the holding current can be obtained using the approximate expression for multiplication s)=[ s B) This equation may be inserted in Equation 2. Approximating the right-hand side of Equation 2 by a straight line of positive slope in the neighborhood of L, leads to where the coefiicient A is the sum of the derivatives of a and in respect to I in the neighborhood of I This equation leads to a proportionality between the deviation of the current from holding current and the voltage, as represented by I I= (V /V or 5 Since n is usually about 2 or 3, this relationship leads to a vertical slope on the V-I plot in the neighborhood of I (Other effects related to space-charge widening may cause this shape to be altered so that a horizontal to the axis is obtained; see Subsection 1D.)

This theory of the conventional four-layer diode shows that adjustment of the values of I and I can lead to a wide variety of shapes of curves like FIG. 1.5. For example, if 1 corresponds to an a behavior in which rises to values near unity at relatively low currents, whereas I is very much larger, then a substantial initial drop in voltage followed by a long plateau will occur, leading to a very high holding current. Characteristics of this sort are desirable for making voltage regulators and other applications.

1C.A transistor diode with negative resistance not using avalan'che but instead using space-charge narrowing of a base layer FIGURE 1.6 illustrates a type of tour-layer diode in which avalanche multiplication plays no significant role. In this case, it is supposed that one of the base layers is sufficiently weakly doped and narrow that the space charge layer of the collector penetrates it to a significant degree. The base and emitter structure on the righthand side of FIG. 1.6 are treated mathematically as a hook collector which gives hook-collector multiplication. (See W. Shockley, Electrons and Holes in Semiconductors, D. Van Nostrand, 1950.) The multiplication in a hook collector can be derived by considering the induced current produced by current flowing into the base layer of the hook collector. For a transistor this multiplication is represented by the well-known relationship a/ (1a)=ratio of induced collector current to base current The actual multiplication of current arriving across the collector junction is obtained by adding the original current to the induced current, thus obtaining for the multiplication in the hook collector the expression L hook 1 12 Substituting Equation 2 into Equation 3 leads readily to L-l-R= (4) This latter result could have been obtained equally well from Equation 1 of Subsection 1.3 for the four-layer diode by setting M equal to unity and neglecting I in comparison to I.

Equation 4 now involves both current and voltage. The simplifying assumptions that voltage has no efiect upon a and current no effect upon ct permit it to be shown that Equation 4 will lead to a negative resistance characteristic when the efiect of space-charge widening upon 04 is considered as follows: To a first approximation, the or of a junction transistor may be taken to vary inversely as the base-layer thickness. This is true for a silicon junction operating under conditions in which the loss of transmitted current occurs chiefly because of recombination at the emitter junction. Assuming this relationship, we conclude WQ (W) :l

where W is the total width of the region b and W(V,,) is the remaining width left after space-charge penetration has been taken into account. Since, in a p-n junction, the voltage across the junction varies approximately the second or third power of the width of the space-charge layer, it is evident that the narrowing of the layer will depend upon the 1/ n power of the voltage where n is of the order of 2 or 3. This is represented by the term in the denominator of Equation 5. The voltage V is the so-called punch-through voltage and is the voltage at which spacecharge widening would lead the space charge to penetrate completely through the base layer 12 In the neighborhood of the holding current I at which a +ot equals unity for V equals zero, the dependence of the alphas upon current may be represented by a linear term and the dependence of a upon voltage may be obtained by taking the first term in the expansion of Equation 5. Then for I slight less than i Equation 4 becomes This should be compared with Equation 5 of LB, discussed earlier, in which it was seen that the current deviation depended upon the square or higher power of voltage, whereas in Equation 7 the voltage depends upon the square or higher power of the current deviation.

The etIect shown in Equation 7 of space-charge narrowing of a base layer can aitect the current voltage characteristic of a tour-layer diode employing avalanche multiplication, and will tend to alter the vertical approach to I represented in FIG. 1.5 and replace it by a tangential approach to the current axis like that shown for FIG. 1.7. FIGURE 1.7 corresponds to a case in which I and I have comparable influences upon the curve like that of FIG. 1.4 so that the plateau is largely missing.

In the following subsection a case of hook-multiplication without avalanche multiplication will be treated in detail as an illustration of design theory.

1D.Symmetricztl hook collector transistor diode As a more complete example of design theory for transistor diodes not using avalanche multiplication, we shall consider a p-n-p-n diode which is symmetrical in the sense that the alphas of the two transistors are assumed to be the same function of current and voltage.

As a basis for an analytical treatment, it is assumed that over the range of interest the current injected into the base and emitter bodies varies as the Boltzmann factor of the voltage across the emitter junction, that is as I (injected) 51 a exp (qV /kT) (1) where V is taken as zero so that V is the forward bias on the base. It is also assumed, in keeping with results obtained by Sah, Noyce, and Shockley, Carrier Generation and Recombination in p n Junctions and p-n Junction Characteristics, Proc. IRE, vol. 45, N0. 9, pp- 1228-1243, September 1957, Equation 30, that the current recombining in the transition region varies as the Boltzmann factor of half the voltage:

I (combining in transition regiomzlia. exp (qVb/2kT) (2) It should be noted that since I varies as the zeroth power of the Boltzmann factor of half the voltage, i.e., is constant, the subscripts of Equation 3 add up as would exponents.

The total current across the junction is This equation is a quadratic in 1 and may be solved to give The ratio of total injected current to total emitter current is denoted by The quantity '7 may be written in a convenient form by the following manipulations:

so that 72 may be expressed as a function /1 of 1/1 a o/Io) The expression for 72 has the following limiting forms:

It will be shown below that the current voltage characteristic may be determined in terms of the functional form of 'y when the dependence of the current I upon the voltage V is taken into account.

The next step in development consists of deriving an expression for the alpha of the emitter base collector structure as a function of the total current flowing through the structure and the voltage across the collector junction. The latter voltage produces the space-charge widening, with resultant narrowing of the base layer, and thus aifects the transmission of minority holes through the base layer. By definition, the quantity or is a(I, Va)=l(minority holes to depletion layer edge)/I (14) 14 Several steps are necessary in determining the functional dependence of a upon the variables I and V The total current carried by injection is composed of two parts, denoted by I2, and 1 representing, respectively, the injected currents that flow into the emitter body and into the base layer:

2= 2E+ 2b The flow into the emitter body is independent of bias across the collector junction and in keeping with Equa tion 1 may be written in the form where 1 is a constant for the structure at a given temperature, and v, is the thermal voltage v =kT/q (17) The current injected into the base layer depends upon the thickness of the base layer and thus upon the voltage across the collector junction. It may be expressed in the form zb abo s) 1 b o) In accordance with the assumption of Equation 2, the current combining in the transition region may be written as 1= 1o P b a) In terms of Equations 15 and 19 and the definition of Equation 3, it follows that The dependence of I2 (V upon voltage is derived below.

Several factors are involved in evaluating a of Equation 14. One of these is the minority transmission factor BO/ for the base layer. This quantity is defined as follows:

fi(Vs)=I (minority holes to depletion layer edge)/I2b (21) In terms of MV a may be Written in the form u(I,V )=B(V )1 /l =fi( s) 2b 2)( z In this equation the ratio in the second factor is the emitter efficiency in terms of injection current alone. It is represented by the symbol 'y* (V where 'Y s) 2b 2= 2bo( s) 2b0( s) 2E0] 'Y2[ o( s) 1 s) p( s)'Y s) In this equation the quantity or now has the value so that Equation 24 involves the current, I, only in the term to the left of the equal sign. In this term the current, I, enters only in terms of a ratio with the current I which is a function of V Making use of the functional relationship for v given in Equation 9, Equation 24 may be solved for I assuming that a= /2. The result is The right-hand side of Equation 26 is a function of V only and may be expressed in analytic form for a particular junction structure. Thus Equation 26 contains the desired current voltage relationship. 

